Conventionally known universal logic modules include a general field programmable gate array (FPGA) and a mask programmable function block based gate array, as just a few examples.
A universal logic module is a semiconductor device that enables the configuration of an ASIC (application specific integrated circuit) including desired built-in logic circuits. A configuration is built in such a manner that transistors (for example, MOS (metal-oxide-semiconductor) transistors) formed on a semiconductor substrate are electrically connected via m wiring layers (m represents an integer equal to or greater than one). In this way, basic circuits called “universal logic cells” are configured in a logic array. Then, with the above configuration being used as a base, the universal logic cells are electrically connected using n wiring layers (n represents an integer equal to or greater than 1). Generally, the basic circuit includes logic circuits having small-scale logic functions, such as inverter circuits, NAND circuits, NOR circuit, and multiplexers, for example.
When the universal logic module is used, wiring patterns of the n layers can be designed to realize desired logic circuits and a semiconductor chip (integrated circuit) on which the desired logic circuits are formed can be obtained according to a semiconductor manufacturing procedure. In this case, the manufacturing procedure uses lithography masks on which the desired m wiring patterns are printed and the n wiring layers can be formed on a semiconductor substrate on which the base configuration has been formed.
The universal logic module is used as described hereunder. For example, a semiconductor manufacturer discloses information of the base configuration to a user. The user then designs the desired logic circuits according to the information disclosed and requests the semiconductor manufacturer to manufacture a semiconductor chip that includes the desired logic circuits. In response, the semiconductor manufacturer performs automatic design of patterns of the n wiring layers in compliance with the requirements received from the user for the desired logic circuits. Then, the manufacturer manufactures the semiconductor chip.
As a universal logic module of the type describe above, for example, Japanese Patent Application Laid-open No. Hei 7-106949 (U.S. Pat. No. 5,055,718) discloses a “Universal Combinatory Logic Module” consisting of a four-input multiplexer (MUX) formed by combining three two-input multiplexers. As a universal logic module of another type, U.S. Pat. No. 5,684,412 discloses a “Cell Forming Part of a Customizable Array.” Further, Japanese Patent Application Laid-open No. Sho 61-61437 discloses a master-slice type integrated circuit that uses storage areas not used for logic functions to work as by-pass capacitors between VDD and GND. Furthermore, Japanese Patent Application Laid-open No. Hei 2-241061 discloses a CMOS gate array that includes noise-absorbing by-pass capacitor between a power supply potential and a ground potential.
In the above-mentioned conventional universal logic modules, MOS transistors included in universal logic cells include those individually pre-connected to a power supply (VDD) line and a ground (GND) line. Thus, the MOS transistor includes a leak current between the source and a drain. Thus, leak currents occur in MOS transistors that are in non-connected or non-used circuits included in the universal logic cell.
Referring now to FIG. 3, a table illustrating the relationships among gate lengths (Leff), power supply voltage (Vcc), and an off-leak current (Ioff) of MOS transistors is set forth. An off-leak current is a leak current when the MOS transistor is turned off. As shown in FIG. 3, the off-leak current increases as the gate length decreases even if the power supply voltage decreases. Therefore, in recent years miniaturization has reached an advanced level where current consumption due to off-leak current cannot be ignored.
Reportedly, when logic circuits are formed using a universal logic module in which a large number of universal logic cells are integrated, the ratio universal logic cells actually used to non-used universal logic cells is about 50%. Hence, the not-used universal logic cells use a large amount of power in a universal logic module.
In addition, the operating frequency of an ASIC in recent years has increased. The increase in operating frequency results in an increase in noise generated in power lines due to the switching operation of transistors, such as MOS transistors, in a universal logic module. This increase noise generated in power lines can cause improper operations or malfunctions.
In view of the above discussion, it would be desirable to provide a universal logic module that may prevent leak current from being generated in a universal logic cell that is not used in a logic circuit and to provide an ASIC using the universal logic module.